FIG. 1 is a block diagram illustrating a conventional read circuit. Referring to FIG. 1, a conventional read circuit includes a precharge current generating circuit 10 and a plurality of sense amplifier circuits 20-1 to 20-n. The sense amplifier circuits 20-1 to 20-n receive a precharge bar signal ‘Prechargeb’ from a control circuit (not shown) of a semiconductor memory device, respectively. The precharge current generating circuit 10 generates a bias signal and provides the generated bias signal to the sense amplifier circuits 20-1 to 20-n, respectively.
FIG. 2 is a circuit diagram of the conventional sense amplifier circuits 20-1 to 20-n shown in FIG. 1. Each of the conventional sense amplifier circuits 20-1 to 20-n may have the structure shown in FIG. 2.
Referring to FIG. 2, the source of a PMOS transistor 22 receives a supply voltage, and the gate of the PMOS transistor 22 receives a bias signal ‘Bias’. The source of a PMOS transistor 27 receives the supply voltage, and the gate of the PMOS transistor 27 receives a precharge bar signal ‘Prechargeb’. The drain of each of the PMOS transistors 22 and 27 is connected to an input terminal of an amplifier 26. The drain of an NMOS transistor 24 is connected to the input terminal of the amplifier 26. The gate of the NMOS transistor 24 is connected with an output terminal of an inverter 28. The inverter 28 inverts an enable bar signal ‘Enableb’. The source of the NMOS transistor 24 is connected with a global bit line ‘GBL’.
FIG. 3 is a timing diagram illustrating a conventional precharge operation of the sense amplifier circuit shown in FIG. 2.
A conventional read operation of a general sense amplifier circuit will now be described with reference to FIGS. 2 and 3. During a conventional read operation, the inverter 28 inverts the input enable bar signal ‘Enableb’. The inverted enable bar signal ‘Enableb’ is applied to the gate of the NMOS transistor 24. The NMOS transistor 24 is turned on by the inverted enable bar signal ‘Enableb’. Because the NMOS transistor 24 is turned on, the global bit line ‘GBL’ is connected to the input terminal of the amplifier 26. During a precharge period, the precharge bar signal ‘Prechargeb’ is applied to the gate of the PMOS transistor 27 causing the PMOS transistor 27 to turn on. Because the PMOS transistor 27 is turned on, a node A of the input terminal of the amplifier 26 is charged to supply voltage VDD and the global bit line ‘GBL’ is charged to a given or predetermined level, as shown in FIG. 3.
After the precharge period ends, during a sensing period, bias signal “Bias’ is applied to the gate of the PMOS transistor 22. While the bias signal is applied to the gate of the PMOS transistor 22, the voltage levels of the global bit line GBL and node A of the input terminal of the amplifier 26 are maintained by a turn-on current of the PMOS transistor 22. The voltage level of the bias signal ‘Bias’ is higher than that of the global bit line GBL, but lower than the supply voltage VDD.
Because each of the sense amplifier circuits 20-1 to 20-n shown in FIG. 1 includes the precharge PMOS transistor 27, the layout area of each of the sense amplifier circuits 20-1 to 20-n increases. Accordingly, the overall size of the memory device increases. In addition, a parasitic capacitance increases due to the precharge transistor, so that the read operation speed decreases.